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| april 20, 2005 ? cypress semiconductor corp. 2004-2005 ? document no. 38-12025 rev. *g 1 psoc? mixed-signal array final data sheet cy8c21234, cy8c21334, cy8c21434, cy8c21534, and cy8c21634 psoc? functional overview the psoc? family consists of many mixed-signal array with on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, as well as programmable interconnect. this architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. addi- tionally, a fast cpu, flash program memory, sram data mem- ory, and configurable io are included in a range of convenient pinouts. the psoc architecture, as illustrated on the left, is comprised of four main areas: the core, the system resources, the digital system, and the analog system. configurable global bus resources allow all the device resources to be combined into a complete custom system. each cy8c21x34 psoc device includes four digital blocks and four analog blocks. depending on the psoc package, up to 28 general purpose io (gpio) are also included. the gpio provide access to the global digital and analog interconnects. the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (inter- nal main oscillator) and ilo (internal low speed oscillator). the features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? low power at high speed ? 2.4v to 5.25v operating voltage ? operating voltages down to 1.0v using on-chip switch mode pump (smp) ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? 4 analog type ?e? psoc blocks provide: - 2 comparators with dac refs - single or dual 8-bit 28 channel adc ? 4 digital psoc blocks provide: - 8- to 32-bit timers, counters, and pwms - crc and prs modules - full-duplex uart, spi ? master or slave - connectable to all gpio pins ? complex peripherals by combining blocks flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 512 bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc? designer) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 25 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 8 analog inputs on gpio ? configurable interrupt on all gpio versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations ? capacitive sensing application capability additional system resources ? i 2 c? master, slave and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference digital system sram 512 bytes system bus interrupt controller clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 8k system resources analog system analog re f . digital cloc ks i2c por and lvd system resets inter nal voltage ref . sw itch mode pump por t 1 po r t 0 sleep and watchdog analog mux po r t 3 por t 2 analog psoc block array digital psoc block array
april 20, 2005 document no. 38-12025 rev. *g 2 cy8c21x34 final data sheet psoc? overview cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8-bit harvard architec- ture microprocessor. system resources provide additional capability, such as digital clocks to increase the flexibility of the psoc mixed-signal arrays, i2c functionality for implementing an i2c master, slave, multimaster, an internal voltage reference that provides an absolute value of 1.3v to a number of psoc subsystems, a switch mode pump (smp) that generates normal operating volt- ages off a single battery cell, and various system resets sup- ported by the m8c. the digital system is composed of an array of digital psoc blocks, which can be configured into any number of digital peripherals. the digital blocks can be connected to the gpio through a series of global buses that can route any signal to any pin. freeing designs from the constraints of a fixed peripheral controller. the analog system is composed of four analog psoc blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. the digital system the digital system is composed of 4 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital peripheral configura- tions include those listed below. pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave and multi-master cyclical redundancy checker/generator (8 to 32 bit) irda pseudo random sequence generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the con- straints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the opti- mum choice of system resources for your application. family resources are shown in the table titled ?psoc device charac- teristics? on page 3 . digital system block diagram the analog system the analog system is composed of 4 configurable blocks, allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the common psoc analog functions for this device (most available as user mod- ules) are listed below. analog-to-digital converters (single or dual, with 8-bit resolu- tion) pin-to-pin comparator single-ended comparators (up to 2) with absolute (1.3v) ref- erence or 8-bit dac reference 1.3v reference (as a system resource) in most psoc devices, analog blocks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. the cy8c21x34 devices provide limited functionality type ?e? analog blocks. each column con- tains one ct type e block and one sc type e block. refer to the psoc mixed-signal array technical reference manual for detailed information on the cy8c21x34?s type e analog blocks. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 ro w 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 3 port 2 port 1 port 0 april 20, 2005 document no. 38-12025 rev. *g 3 cy8c21x34 final data sheet psoc? overview analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins can be connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with com- parators and analog-to-digital converters. an additional 8:1 ana- log input multiplexer provides a second path to bring port 0 pins to the analog array. switch control logic enables selected pins to precharge continu- ously under hardware control. this enables capacitive mea- surement for applications such as touch sensing. other multiplexer applications include: track pad, finger sensing. chip-wide mux that allows analog input from any io pin. crosspoint connection between any io pin combinations. additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. addi- tional resources include a switch mode pump, low voltage detection, and power on reset. brief statements describing the merits of each system resource are presented below. digital clock dividers provide three customizable clock fre- quencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute refer- ence for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. versatile analog multiplexer system. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. the following table lists the resources available for specific psoc device groups. the psoc device covered by this data sheet is highlighted below. ac ol1m u x ace00 ace01 array array input configuration ase10 ase11 x x x x x analo g mux bus all io aci0[1:0] aci1[1:0] psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 12 4 4 12 2k 32k cy8c27x43 up to 44 2 8 12 4 4 12 256 bytes 16k cy8c24794 50 1 4 48 2 2 6 1k 16k cy8c24x23 up to 24 1 4 12 2 2 6 256 bytes 4k cy8c24x23a up to 24 1 4 12 2 2 6 256 bytes 4k cy8c21x34 up to 28 1 4 28 0 2 4 a a. limited analog functionality . 512 bytes 8k cy8c21x23 16 1 4 8 0 2 4 a 256 bytes 4k april 20, 2005 document no. 38-12025 rev. *g 4 cy8c21x34 final data sheet psoc? overview getting started the quickest path to understanding the psoc silicon is by read- ing this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an over- view of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc mixed-signal array technical reference manual , which can be found on http://www.cypress.com/psoc. for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com, click the online store shopping cart icon at the bottom of the web page, and click psoc (program- mable system-on-chip) to view a current list of available items. technical training free psoc technical training is available for beginners and is taught by a marketing or application engineer over the phone. psoc training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as psoc and the lin bus. go to http://www.cypress.com, click on design support located on the left side of the web page, and select technical training for more details. consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com, click on design support located on the left side of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are sorted by date by default. development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on- chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (reference the psoc designer func- tional flow diagram below.) psoc designer helps the customer to select an operating con- figuration for the psoc, write application code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. psoc designer subsystems commands results psoc tm designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interf ac e context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc tm designer april 20, 2005 document no. 38-12025 rev. *g 5 cy8c21x34 final data sheet psoc? overview psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfig- uration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the psoc family of devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. april 20, 2005 document no. 38-12025 rev. *g 6 cy8c21x34 final data sheet psoc? overview designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the io pins. iterative development cycles permit you to adapt the hard- ware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer inte- grated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library con- tains over 50 common peripherals such as adcs, dacs tim- ers, counters, uarts, and other not-so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user mod- ule configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high- level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the set- ting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. user module and source code development flows the next step is to write your main program, and any sub-rou- tines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all gener- ated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a profes- sional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as nec- essary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger down- loads the hex image to the in-circuit emulator (ice) where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator april 20, 2005 document no. 38-12025 rev. *g 7 cy8c21x34 final data sheet psoc? overview document conventions acronyms used the following table lists the acronyms that are used in this doc- ument. units of measure a units of measure table is located in the electrical specifica- tions section. table 3-1 on page 15 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. table of contents for an in depth discussion and more information on your psoc device, obtain the psoc mixed-signal array technical refer- ence manual on http://www.cypress.com . this document encompasses and is organized into the following chapters and sections. 1. pin information ............................................................. 8 1.1 pinouts ................................................................... 8 1.1.1 16-pin part pinout ..................................... 8 1.1.2 20-pin part pinout ..................................... 9 1.1.3 28-pin part pinout ................................... 10 1.1.4 32-pin part pinout ................................... 11 2. register reference ..................................................... 12 2.1 register conventions ........................................... 12 2.2 register mapping tables ..................................... 12 3. electrical specifications ............................................ 15 3.1 absolute maximum ratings ................................. 16 3.2 operating temperature ........................................ 16 3.3 dc electrical characteristics ................................ 16 3.3.1 dc chip-level specifications ................... 16 3.3.2 dc general purpose io specifications .... 17 3.3.3 dc operational amplifier specifications ... 18 3.3.4 dc switch mode pump specifications ..... 19 3.3.5 dc analog mux bus specifications .......... 20 3.3.6 dc por and lvd specifications ............. 20 3.3.7 dc programming specifications ............... 21 3.4 ac electrical characteristics ................................ 22 3.4.1 ac chip-level specifications ................... 22 3.4.2 ac general purpose io specifications .... 24 3.4.3 ac operational amplifier specifications ... 25 3.4.4 ac analog mux bus specifications .......... 25 3.4.5 ac digital block specifications ................. 25 3.4.6 ac external clock specifications ............. 27 3.4.7 ac programming specifications ............... 28 3.4.8 ac i2c specifications ............................... 28 4. packaging information ............................................... 30 4.1 packaging dimensions ......................................... 30 4.2 thermal impedances .......................................... 32 4.3 solder reflow peak temperature ........................ 33 5. ordering information .................................................. 34 5.1 ordering code definitions .................................... 34 6. sales and service information .................................. 35 6.1 revision history ................................................... 35 6.2 copyrights and code protection .......................... 35 acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor slimo slow imo smp switch mode pump sram static random access memory april 20, 2005 document no. 38-12025 rev. *g 8 1. pin information this chapter describes, lists, and illustrates the cy8c21x34 psoc device pins and pinout configurations. 1.1 pinouts the cy8c21x34 psoc device is available in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital io and connection to the common analog bus. however, vss, vdd, smp, and xres are not capable of digital io. 1.1.1 16-pin part pinout table 1-1. 16-pin part pinout (soic) pin no. type name description cy8c21234 16-pin psoc device digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input. 3 io i, m p0[3] analog column mux input, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 power smp switch mode pump (smp) connection to required external components. 6 power vss ground connection. 7 io m p1[1] i2c serial clock (scl), issp-sclk. 8 power vss ground connection. 9 io m p1[0] i2c serial data (sda), issp-sdata. 10 io m p1[2] 11 io m p1[4] optional external clock input (extclk). 12 io i, m p0[0] analog column mux input. 13 io i, m p0[2] analog column mux input. 14 io i, m p0[4] analog column mux input. 15 io i, m p0[6] analog column mux input. 16 power vdd supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. soic vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p1[4], extclk, m p1[2], m p1[0], i2c sda, m 16 15 14 13 12 11 1 2 3 4 5 6 7 8 a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] smp vss m, i2c scl, p1[1] vss 10 9 april 20, 2005 document no. 38-12025 rev. *g 9 cy8c21x34 final data sheet 1. pin information 1.1.2 20-pin part pinout table 1-2. 20-pin part pinout (ssop) pin no. type name description cy8c21334 20-pin psoc device digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input. 3 io i, m p0[3] analog column mux input, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 power vss ground connection. 6 io m p1[7] i2c serial clock (scl). 7 io m p1[5] i2c serial data (sda). 8 io m p1[3] 9 io m p1[1] i2c serial clock (scl), issp-sclk. 10 power vss ground connection. 11 io m p1[0] i2c serial data (sda), issp-sdata. 12 io m p1[2] 13 io m p1[4] optional external clock input (ext- clk). 14 io m p1[6] 15 input xres active high external reset with internal pull down. 16 io i, m p0[0] analog column mux input. 17 io i, m p0[2] analog column mux input. 18 io i, m p0[4] analog column mux input. 19 io i, m p0[6] analog column mux input. 20 power vdd supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. ssop vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, i2c scl, p1[7] sda, p1[5] m, p1[3] scl, p1[1] vss vss m, i2c m, i2c april 20, 2005 document no. 38-12025 rev. *g 10 cy8c21x34 final data sheet 1. pin information 1.1.3 28-pin part pinout table 1-3. 28-pin part pinout (ssop) pin no. type name description cy8c21534 28-pin psoc device digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input and column output. 3 io i, m p0[3] analog column mux input and column output, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 io m p2[7] 6 io m p2[5] 7 io i, m p2[3] direct switched capacitor block input. 8 io i, m p2[1] direct switched capacitor block input. 9 power vss ground connection. 10 io m p1[7] i2c serial clock (scl). 11 io m p1[5] i2c serial data (sda). 12 io m p1[3] 13 io m p1[1] i2c serial clock (scl), issp-sclk. 14 power vss ground connection. 15 io m p1[0] i2c serial data (sda), issp-sdata. 16 io m p1[2] 17 io m p1[4] optional external clock input (ext- clk). 18 io m p1[6] 19 input xres active high external reset with internal pull down. 20 io i, m p2[0] direct switched capacitor block input. 21 io i, m p2[2] direct switched capacitor block input. 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. legend a: analog, i: input, o = output, and m = analog mux input. a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] vss m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 april 20, 2005 document no. 38-12025 rev. *g 11 cy8c21x34 final data sheet 1. pin information 1.1.4 32-pin part pinout table 1-4. 32-pin part pinout (mlf*) pin no. type name description cy8c21434 32-pin psoc device digital analog 1 io i, m p0[1] analog column mux input, integrating input. 2 io m p2[7] 3 io m p2[5] 4 io m p2[3] 5 io m p2[1] 6 io m p3[3] in cy8c21434 part. 6 power smp switch mode pump (smp) connection to required external components in cy8c21634 part. 7 io m p3[1] in cy8c21434 part. 7 power vss ground connection in cy8c21634 part. 8 io m p1[7] i2c serial clock (scl). 9 io m p1[5] i2c serial data (sda). 10 io m p1[3] 11 io m p1[1] i2c serial clock (scl), issp-sclk. 12 power vss ground connection. 13 io m p1[0] i2c serial data (sda), issp-sdata. 14 io m p1[2] 15 io m p1[4] optional external clock input (extclk). 16 io m p1[6] 17 input xres active high external reset with internal pull down. cy8c21634 32-pin psoc device 18 io m p3[0] 19 io m p3[2] 20 io m p2[0] 21 io m p2[2] 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input. 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. 29 io i, m p0[7] analog column mux input. 30 io i, m p0[5] analog column mux input. 31 io i, m p0[3] analog column mux input, integrating input. 32 power vss ground connection. legend a = analog, i = input, o = output, and m = analog mux input. * the mlf package has a center pad that must be connected to ground (vss). a, i, m, p0[1] m, p2[ 7] m, p2[ 5] m, p2[ 3] m, p2[ 1] m, p3[ 3] mlf (top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[ 1] m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xr e s m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m a, i, m, p0[1] m, p2[ 7] m, p2[ 5] m, p2[ 3] m, p2[ 1] smp mlf (top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xr e s m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m april 20, 2005 document no. 38-12025 rev. *g 12 2. register reference this chapter lists the registers of the cy8c21x34 psoc device. for detailed register information, reference the psoc? mixed-signal array technical reference manual . 2.1 register conventions the register conventions specific to this section are listed in the following table. 2.2 register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific april 20, 2005 document no. 38-12025 rev. *g 13 cy8c21x34 final data sheet 2. register reference register map 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 cur_pp d0 rw 11 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. april 20, 2005 document no. 38-12025 rev. *g 14 cy8c21x34 final data sheet 2. register reference register map 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific. april 20, 2005 document no. 38-12025 rev. *g 15 3. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c21x34 psoc device. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c as specified, except where noted. refer to table 3-14 for the electrical specifications on the internal main oscillator (imo) using slimo mode. figure 3-1a. voltage versus cpu frequency figure 3-1b. imo frequency trim options the following table lists the units of measure that are used in this chapter. table 3-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm ? ohm mhz megahertz pa picoampere m ? megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 april 20, 2005 document no. 38-12025 rev. *g 16 cy8c21x34 final data sheet 3. electrical specifications 3.1 absolute maximum ratings 3.2 operating temperature 3.3 dc electrical characteristics 3.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-2. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 o c higher storage temperatures will reduce data retention time. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 3-3. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 32 . the user must limit the power con- sumption to comply with this requirement. table 3-4. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see table titled ?dc por and lvd specifica- tions? on page 20 . i dd supply current, imo = 24 mhz ? 3 4 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current, imo = 6 mhz using slimo mode. ? 1.2 2 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i dd27 supply current, imo = 6 mhz using slimo mode. ? 1.1 1.5 ma conditions are vdd = 2.55v, t a = 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4. a vdd = 2.55v, 0 o c t a 40 o c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, -40 o c t a 85 o c. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0v to 5.25v. v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v. agnd analog ground v ref - 0.003 v ref v ref + 0.003 v april 20, 2005 document no. 38-12025 rev. *g 17 cy8c21x34 final data sheet 3. electrical specifications 3.3.2 dc general purpose io specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 3-5. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c. table 3-6. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level vdd - 0.4 ? ? v ioh = 2.5 ma (6.25 typ), vdd = 2.4 to 3.0v (16 ma maximum, 50 ma typ combined ioh bud- get). v ol low output level ? ? 0.75 v iol = 10 ma, vdd = 2.4 to 3.0v (90 ma maxi- mum combined iol budget). v il input low level ? ? 0.75 v vdd = 2.4 to 3.0. v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0. v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c. april 20, 2005 document no. 38-12025 rev. *g 18 cy8c21x34 final data sheet 3. electrical specifications 3.3.3 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-7. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa a a. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 na. input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 3-8. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa a a. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 na. input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 3-9. 2.7v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa a a. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 na. input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a april 20, 2005 document no. 38-12025 rev. *g 19 cy8c21x34 final data sheet 3. electrical specifications 3.3.4 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. figure 3-2. basic switch mode pump circuit table 3-10. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump5v 5v output voltage from pump 4.75 5.0 5.25 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 5.0v. v pump3v 3.3v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 3.25v. v pump2v 2.6v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 2.55v. i pump available output current v bat = 1.8v, v pump = 5.0v v bat = 1.5v, v pump = 3.25v v bat = 1.3v, v pump = 2.55v 5 8 8 ? ? ? ? ? ? ma ma ma configuration of footnote. a smp trip voltage is set to 5.0v. smp trip voltage is set to 3.25v. smp trip voltage is set to 2.55v. v bat5v input voltage range from battery 1.8 ? 5.0 v configuration of footnote. a smp trip voltage is set to 5.0v. v bat3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote. a smp trip voltage is set to 3.25v. v bat2v input voltage range from battery 1.0 ? 2.8 v configuration of footnote. a smp trip voltage is set to 2.55v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. a 0 o c t a 100. 1.25v at t a = -40 o c. ? v pump_line line regulation (over vi range) ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 3- 12 on page 20 . ? v pump_load load regulation ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 3- 12 on page 20 . ? v pump_ripple output voltage ripple (depends on cap/load) ? 100 ? mvpp configuration of footnote. a load is 5 ma. a. l 1 = 2 h inductor, c 1 = 10 f capacitor, d 1 = schottky diode. see figure 3-2. e 3 efficiency 35 50 ? % configuration of footnote. a load is 5 ma. smp trip voltage is set to 3.25v. e 2 efficiency 35 80 ? % for i load = 1ma, v pump = 2.55v, v bat = 1.3v, 10 uh inductor, 1 uf capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % battery c1 d1 + psoc t m vdd vss smp v bat l 1 v pump april 20, 2005 document no. 38-12025 rev. *g 20 cy8c21x34 final data sheet 3. electrical specifications 3.3.5 dc analog mux bus specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. 3.3.6 dc por and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-11. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 ? ? vdd 2.7v 2.4v vdd 2.7v r vdd resistance of initialization switch to vdd ? ? 800 ? table 3-12. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lv d0 v lv d1 v lv d2 v lv d3 v lv d4 v lv d5 v lv d6 v lv d7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 a 2.99 b 3.09 3.20 4.55 4.75 4.83 4.95 a. always greater than 50 mv above v ppor (porlev = 00) for falling supply. b. always greater than 50 mv above v ppor (porlev = 01) for falling supply. v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 c 3.09 3.16 3.32 d 4.74 4.83 4.92 5.12 c. always greater than 50 mv above v lvd0 . d. always greater than 50 mv above v lvd3 . v v v v v v v v april 20, 2005 document no. 38-12025 rev. *g 21 cy8c21x34 final data sheet 3. electrical specifications 3.3.7 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-13. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? ye ars april 20, 2005 document no. 38-12025 rev. *g 22 cy8c21x34 final data sheet 3. electrical specifications 3.4 ac electrical characteristics 3.4.1 ac chip-level specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-14. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 a,b,c mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 3-1b on page 15 . slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b,c mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 3-1b on page 15 . slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz 24 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b, c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for in formation on trimming for operation at 3.3v. mhz f blk5 digital psoc block frequency 0 (5v nominal) 0 48 49.2 a,b,d d. see the individual user module data sheets for information on maximum frequencies for user modules. mhz refer to the ac digital block specifica- tions below. f blk33 digital psoc block frequency (3.3v nominal) 0 24 24.6 b,d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32 khz rms period jitter ? 100 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz peak-to-peak period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s table 3-15. 2.7v ac chip-level specifications symbol description min typ max units notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 0 12.7 a,b,c mhz trimmed for 2.7v operation using factory trim values. see figure 3-1b on page 15 . slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b,c mhz trimmed for 2.7v operation using factory trim values. see figure 3-1b on page 15 . slimo mode = 1. f cpu1 cpu frequency (2.7v nominal) 0.093 3 3.15 a,b a. 2.4v < vdd < 3.0v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz 24 mhz only for slimo mode = 0. f blk27 digital psoc block frequency (2.7v nominal) 0 12 12.5 a,b,c c. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on maximu m frequency for user modules. mhz refer to the ac digital block specifica- tions below. f 32k1 internal low speed oscillator frequency 8 32 96 khz jitter32k 32 khz rms period jitter ? 150 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s april 20, 2005 document no. 38-12025 rev. *g 23 cy8c21x34 final data sheet 3. electrical specifications figure 3-3. 24 mhz period jitter (imo) timing diagram figure 3-4. 32 khz period jitter (ilo) timing diagram jitter24m1 f 24m jitter32k f 32k1 april 20, 2005 document no. 38-12025 rev. *g 24 cy8c21x34 final data sheet 3. electrical specifications 3.4.2 ac general purpose io specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. figure 3-5. gpio timing diagram table 3-16. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 3-17. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf tfalls trisef tri se s 90% 10% gpio pin output voltage april 20, 2005 document no. 38-12025 rev. *g 25 cy8c21x34 final data sheet 3. electrical specifications 3.4.3 ac operational amplifier specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. 3.4.4 ac analog mux bus specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. 3.4.5 ac digital block specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-18. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv overdrive 100 200 ns ns vdd 3.0v. 2.4v < vcc < 3.0v. table 3-19. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz table 3-20. 5v and 3.3v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 mhz 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 mhz 3.0v < vdd < 4.75v. timer capture pulse width 50 a ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with or without capture ? ? 24.6 mhz counter enable pulse width 50 ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 ? ? ns april 20, 2005 document no. 38-12025 rev. *g 26 cy8c21x34 final data sheet 3. electrical specifications transmitter maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. receiver maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). table 3-21. 2.7v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency 12.7 mhz 2.4v < vdd < 3.0v. timer capture pulse width 100 a ? ? ns maximum frequency, with or without capture ? ? 12.7 mhz counter enable pulse width 100 ? ? ns maximum frequency, no enable input ? ? 12.7 mhz maximum frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns maximum frequency ? ? 12.7 mhz crcprs (prs mode) maximum input clock frequency ? ? 12.7 mhz crcprs (crc mode) maximum input clock frequency ? ? 12.7 mhz spim maximum input clock frequency ? ? 6.35 mhz maximum data rate at 3.17 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 100 ? ? ns transmitter maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). table 3-20. 5v and 3.3v ac digital block specifications (continued) april 20, 2005 document no. 38-12025 rev. *g 27 cy8c21x34 final data sheet 3. electrical specifications 3.4.6 ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-22. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 3-23. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 3-24. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power up imo to switch 150 ? ? s april 20, 2005 document no. 38-12025 rev. *g 28 cy8c21x34 final data sheet 3. electrical specifications 3.4.7 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. 3.4.8 ac i 2 c specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 3-25. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 < vdd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 table 3-26. ac characteristics of the i 2 c sda and scl pins for vdd 3.0v symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input fil- ter. ? ? 0 50 ns table 3-27. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 ??khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c set-up time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s april 20, 2005 document no. 38-12025 rev. *g 29 cy8c21x34 final data sheet 3. electrical specifications figure 3-6. definition for timing for fast/standard mode on the i 2 c bus t sudati2c data set-up time 250 ? ? ?ns t sustoi2c set-up time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are suppressed by the input fil- ter. ? ???ns table 3-27. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) (continued) symbol description standard mode fast mode units notes min max min max sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c april 20, 2005 document no. 38-12025 rev. *g 30 4. packaging information this chapter illustrates the packaging specifications for the cy8c21x34 psoc device, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support/link.cfm?mr=poddim . 4.1 packaging dimensions figure 4-1. 16-lead (150-mil) soic dimensions in inches[mm] min. max. pin 1 id 0.291[7.391] 0.299[7.594] 0.394[10.007] 0.419[10.642] 0.397[10.083] 0.413[10.490] 0.050[1.270] typ. 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0.299] seating plane 0.0091[0.231] 0.0125[0.317] 0.015[0.381] 0.050[1.270] 0.013[0.330] 0.019[0.482] 0.026[0.660] 0.032[0.812] 0.004[0.101] 1 8 916 * * * * reference jedec mo-119 part # s16.3 standard pkg. sz16.3 lead free pkg. 51-85022 *b april 20, 2005 document no. 38-12025 rev. *g 31 cy8c21x34 final data sheet 4. packaging information figure 4-2. 20-lead (210-mil) ssop figure 4-3. 28-lead (210-mil) ssop 51-85077 *c 51-85079 - *c april 20, 2005 document no. 38-12025 rev. *g 32 cy8c21x34 final data sheet 4. packaging information figure 4-4. 32-lead (5x5 mm) mlf important note for information on the preferred dimensions for mounting mlf packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . 4.2 thermal impedances table 4-1. thermal impedances per package package typical ja * typical jc 16 soic 123 o c/w 55 o c/w 20 ssop 117 o c/w 41 o c/w 28 ssop 96 o c/w 39 o c/w 32 mlf 22 o c/w 12 o c/w * t j = t a + power x ja 51-85188 ** e-pad x, y for this product is 3.71 mm, 3.71 mm ( +/- 0.08 mm) april 20, 2005 document no. 38-12025 rev. *g 33 cy8c21x34 final data sheet 4. packaging information 4.3 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 4-2. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 16 soic 240 o c 260 o c 20 ssop 240 o c 260 o c 28 ssop 240 o c 260 o c 32 mlf 240 o c 260 o c *higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220+/-5 o c with sn-pb or 245+/-5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. april 20, 2005 document no. 38-12025 rev. *g 34 5. ordering information the following table lists the cy8c21x34 psoc device?s key package features and ordering codes. 5.1 ordering code definitions cy8c21x34 psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) switch mode pump temperature range digital blocks analog blocks digital io pins analog inputs a analog outputs xres pin 16 pin (150-mil) soic cy8c21234-24sxi 8k 512 ye s -40 c to +85 c 4 4 12 12 a a. all digital io pins also connect to the common analog mux. 0 no 16 pin (150-mil) soic (tape and reel) cy8c21234-24sxit 8k 512 ye s -40 c to +85 c 4 4 12 12 a 0 no 20 pin (210-mil) ssop cy8c21334-24pvxi 8k 512 no -40 c to +85 c 4 4 16 16 a 0 yes 20 pin (210-mil) ssop (tape and reel) cy8c21334-24pvxit 8k 512 no -40 c to +85 c 4 4 16 16 a 0 yes 28 pin (210-mil) ssop cy8c21534-24pvxi 8k 512 no -40 c to +85 c 4 4 24 24 a 0 yes 28 pin (210-mil) ssop (tape and reel) cy8c21534-24pvxit 8k 512 no -40 c to +85 c 4 4 24 24 a 0 yes 32 pin (5x5) mlf b b. refer to the ?32-pin part pinout? on page 11 for pin differences. cy8c21434-24lfxi 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5) mlf b (tape and reel) cy8c21434-24lfxit 8k 512 no -40 c to +85 c 4 4 28 28 a 0 yes 32 pin (5x5) mlf b cy8c21634-24lfxi 8k 512 ye s -40 c to +85 c 4 4 26 26 a 0 yes 32 pin (5x5) mlf b (tape and reel) cy8c21634-24lfxit 8k 512 ye s -40 c to +85 c 4 4 26 26 a 0 yes c y 8 c 21 xxx-24xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx = mlf pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress microsystems company id: cy = cypress april 20, 2005 ? cypress semiconductor corp. 2004-2005 ? document no. 38-12025 rev. *g 35 6. sales and service information to obtain information about cypress semiconductor or psoc sales and technical support, reference the following information. cypress semiconductor 6.1 revision history 6.2 copyrights and code protection copyrights ? cypress semiconductor corp. 2004-2005. all rights reserved. psoc?, psoc designer?, and programmable system-on-chip? are psoc- related trade- marks of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respec tive corporations. the information contained herein is subject to change without notice. cypress semiconductor assumes no responsibility for the u se of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license under patent or other rights. cypress semi conductor does not authorize its prod- ucts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclu- sion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of su ch use and in doing so indemnifies cypress semiconductor against all charges. cypress semiconductor products are not warranted nor intended to be used for medical , life-support, life-saving, critical con- trol or safety applications, unless pursuant to an express written agreement with cypress semiconductor. flash code protection note the following details of the flash code protection features on cypress semiconductor psoc devices. cypress semiconductor products meet the specifications contained in their particular data sheets. cypress semiconductor believe s that its psoc family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress semiconductor, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress semiconductor nor any other semicon- ductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the produc t as "unbreakable." cypress semiconductor is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress semiconductor are committed to continuously improving the code protection features of our products. 2700 162nd street sw, building d phone: 800.669.0557 lynnwood, wa 98037 facsimile: 425.787.4641 web sites: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm document title : cy8c21234, cy8c21334, cy8c21434, cy8c21534, and cy8c21634 psoc mixed-signal array final data sheet document number : 38-12025 revision ecn # issue date origin of change description of change ** 227340 5/19/2004 hmt new silicon and document (revision **). *a 235992 see ecn sfv updated overview and electrical spec. chapters, along with revisions to the 24-pin pinout part. revised the register mapping tables. added a ssop 28-pin part. *b 248572 see ecn sfv changed title to include all part #s. changed 28-pin ssop from cy8c21434 to cy8c21534. changed pin 9 on the 28-pin ssop from smp pin to vss pin. added smp block to architecture diagram. update electrical specificati ons. added another 32-pin mlf part: cy8c21634. *c 277832 see ecn hmt verify data sheet standards from sfv memo. add analog input mux to applicable pin outs. update psoc characteristics table. update diagrams and specs. final. *d 285293 see ecn hmt update 2.7v dc gpio spec. a dd reflow peak temp. table. *e 301739 see ecn hmt dc chip-level specification changes. update links to new cy.com portal. *f 329104 see ecn hmt re-add pinout issp notation. fix tmp register names. clarify adc feature. update electrical specifications. update reflow peak temp. table. add 32 mlf e-pad dimensions. add thetajc to thermal impedance table. fix 20-pin package order number. add cy logo. update cy copyright. *g 352736 see ecn hmt add new color and logo. add url to preferred dimensions for mounting mlf packages. update transmitter and receiver ac digital block electrical specifications. distribution : external/public posting : none |
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